Phase-locked loop (“PLL”) circuitry is used in frequency or clocking signal generation typically to generate signals relative to an input reference signal, such as a crystal oscillator, an inductive-capacititive (“LC”) oscillator, a resistive-capacititive (“RC”) oscillator or another type of relaxation oscillator. The phase-locked loop circuitry adjusts the frequency of a PLL output signal based on frequency and/or phase differences between the reference signal and the output signal. Based on any such difference, the frequency and/or phase of the output signal is increased or decreased accordingly. Phase-locked loops are used in a wide range of electronics, such as radios, telecommunication circuits, wireless and mobile devices, computers, and other devices.
Many such PLLs are either not configurable or not reconfigurable, so are more difficult to use with or within configurable or reconfigurable circuitry such as field programmable gate arrays (“FPGAs”) or other logic circuitry. For example, such PLLs may not be configurable for a wide frequency range (especially at comparatively high frequencies), desired jitter level or specification, fractional frequency generation, power usage or dissipation, oscillation quality (“Q”) factor, and so on, particularly while maintaining accuracy and avoiding frequency drift, including over fabrication process, voltage, and temperature (“PVT”) variations.
In addition, the circuit designs of many PLLs, such as those which may be provided by a foundry to insert into the design of an integrated circuit for a selected silicon fabrication process technology, have a fixed IC layout (or floorplan). Such PLLs are provided as a “black box” design having a predetermined IC layout (or floorplan), a predetermined IC layout aspect ratio, and predetermined IC locations for circuitry inputs and outputs, for example. As a result, these “black box” PLLs cannot be readily inserted into any selected IC design without accommodating this fixed floorplan and significantly affecting the overall IC area and timing, and cannot be utilized independently of the silicon fabrication process technology.
As a consequence, a need remains for a reconfigurable, digital phase-locked loop which generates a frequency reference or delay with phase detection or measurement and which is configurable or reconfigurable for a variety of parameters and options, such as frequency, bandwidth, frequency resolution, jitter level or scale, power consumption, and/or fractional frequencies, and various options, such as inclusion of an LC oscillator.
In addition, such a reconfigurable, digital PLL should be capable of being provided as a circuitry netlist (generated using Verilog as an IC design tool, for example) or other comparable circuit specification, to produce a reconfigurable, digital PLL having a selected, malleable or otherwise variable IC layout (or floorplan), rather than a fixed or predetermined IC layout (or floorplan). Such a reconfigurable, digital PLL should also be readily insertable into virtually any selected IC design with either no or comparatively minor modification.
Lastly, such a reconfigurable, digital PLL should provide for control over output frequency, to provide a stable and desired frequency in response to variation in ambient or junction temperature or variation in other parameters such as voltage, fabrication process, frequency, and age.